ADC10D1500CIUT/NOPB

Product Summary

The ADC10D1500CIUT/NOPB is an nationals utra-high-speed ADC. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1500CIUT/NOPB builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set of the ADC10D1500CIUT/NOPB includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is guaranteed to have no missing codes over the full operating temperature range.

Parametrics

ADC10D1500CIUT/NOPB absolute maximum ratings: (1)Supply Voltage (VA, VTC, VDR, VE): 2.2V; (2)Supply Difference max(VA/TC/DR/E)- min(VA/TC/DR/E): 0V to 100 mV; (3)Voltage on Any Input Pin (except VIN+/-): -0.15V to (VA + 0.15V); (4)VIN+/- Voltage Range: -0.15V to 2.5V; (5)Ground Difference max(GNDTC/DR/E)-min(GNDTC/DR/E): 0V to 100 mV; (6)Input Current at Any Pin: ±50 mA; (7)ADC10D1000 Package Power Dissipation at TA ≤ 85℃: 3.7 W; (8)ADC10D1500 Package Power Dissipation at TA ≤ 70℃: 4.4 W; (9)ESD Susceptibility Human Body Model: 2500V; (10)Storage Temperature: -65℃ to +150℃.

Features

ADC10D1500CIUT/NOPB features: (1)Excellent accuracy and dynamic performance; (2)Low power consumption, further reduced at lower Fs; (3)Internally terminated, buffered, differential analog inputs; (4)R/W SPI Interface for Extended Control Mode; (5)Dual-Edge Sampling Mode, in which the I- and Q-channels sample one input at twice the sampling clock rate; (6)Test patterns at output for system debug; (7)Programmable 15-bit gain and 12-bit plus sign offset; (8)Programmable tAD adjust feature; (9)1:1 non-demuxed or 1:2 demuxed LVDS outputs; (10)AutoSync feature for multi-chip systems; (11)Single 1.9V ± 0.1V power supply; (12)292-ball BGA package (27mm x 27mm x 2.4mm with 1.27mm ball-pitch); no heat sink required; (13)LC sampling clock filter for jitter reduction.

Diagrams